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Senior (or junior) Power Engineer

8.3-16.6K
  • 五险一金
  • 员工福利
  • 8小时工作制

2019年5月16日刷新

Senior (or junior) Power Engineer

8.3-16.6K
  • 五险一金
  • 员工福利
  • 8小时工作制
职位已过期

捷普集团 JABIL

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 SUMMARY 



Take the major responsibility for Signal integrity design Telecom and networking projects. Provide necessary inputs regarding high-speed signal quality and design constraints to electronics designers for signal & design quality assurance. Drive innovation and continuous improvement within Jabil Circuit by harnessing new technologies and methodologies. Provide exceptional support to external and internal customers, team members, and other persons through technical project coordination. 



ESSENTIAL DUTIES AND RESPONSIBILITIES include, but are not limited to the following: 

 Lead the SI/SPIT team

 Responsible for the high-speed signal pre-simulation and post-simulation, layout constraints preparation, and PCB design

 Perform system level’s signal integrity and timing analysis on boards, packages, connectors and ASICs etc.

 Cooperate with SPIT(Signal, Integrity, Power, and Timing) engineers to develop SPIT Test plans and basic bring-up/functionality testing plans

 Correlate SI simulations with SPIT measurements to validate the modeling methodology

 Contribute to the design trade-offs and evaluation of mechanical, electrical, and thermal performance of both components level and system level

 Cooperate with electronics engineers for signal issues & Lab debug



REQUIREMENTS:

 Master Degree in Engineering or Equivalent with at least 4 years related experience in Hi-Speed signal simulation

 Proficient with board level’s reflection, x-talk, ground bounce, bypassing techniques for power/ground noise reduction, termination techniques for reflection noise control

 Proficient with on chip SI including core noise modeling, on chip crosstalk, I/O selection, chip pin-out assignment, package selection and pin-out arrangement

 Proficient with PCB cross-section design and trade-off, SERDES channel analysis and PCB stack-up calculation etc.

 Proficient with high speed connectors and board to board interconnect.

 Proficient with 2-D/3-D CAD tools such as SpectreQuest, Hspice and competent for SPIT (Signal, Integrity, power, and Timing) Measurement 

 Good working knowledge in various electronics test and measurement instruments like signal generators, logic analyzer, network analyzer, bus protocols analyzer, and oscilloscope etc.

 Experience with multiple high-speed traces on a single board (ex PCI-E gen 3, DDR III/IV, 25Gbps or 56G PAM4 traces)

 Experience of working in medium sized multidisciplinary development teams 

 Good English Speaking and literacy


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  • 年龄要求: 不限
  • 语言要求: 不限
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